1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a method of forming a virtual-ground split-gate erasable programmable read only memory (EPROM) cell.
2. Description of the Related Art
Virtual-ground split-gate EPROM cells have been proposed as a means for improving the packing density and yield of EPROM of the prior art. These virtual-ground split-gate EPROM cells offer two important advantages in that they employ buried N.sup.+ bit lines and provide a series select transistor associated with each floating gate. The use of buried N.sup.+ bit lines greatly reduces the number of contacts needed in the memory array and directly improves packing density and yield. In addition, by providing a series select transistor associated with each floating gate, voltage arising in the bit line voltage is impressed to floating gates of nonselected memory cells connected to selected bit lines, thereby insuring that nonselected memory cells are not inadvertently turned on and greatly relieving constraints on drain write voltage.
This type of memory cell has conventionally been formed by the memory cell fabrication process shown in FIG. 1. Photoresist mask pattern 3, which defines the position of a buried N.sup.+ diffused layer, is first formed on silicon substrate 1, and ion injection of impurities is then carried out to form a buried N.sup.+ diffused layer by means of this mask pattern 3 (Refer to FIG. 1A). After removal of the photoresist, polysilicon film 5 for floating gate use stacked over gate oxidation film 4 is next processed into gate form by dry etching employing photoresist mask pattern 6 (Refer to FIG. 1B). After successively forming intergate insulation film 8 and an overlying polysilicon film 7, polysilicon film 7 is formed for control gate use over the surface of the element (Refer to FIG. 1C). Following these processes, nonvolatile memory elements are produced by carrying out subsequent steps such as normal wiring processes.
This virtual-ground split-gate EPROM has the several drawbacks. First, because the channel length of a series select transistor is defined by the masking of the buried N.sup.+ diffused layer, the electrical characteristics of a series select transistor are greatly affected by the alignment of the N.sup.+ diffused layer with respect to the floating polysilicon gate. Second, the cell characteristics are further affected by variations in the series resistance of the buried bit line originating in misalignment of the final position of the buried N.sup.+ diffused layer region. Third, the overall packing density tends to be reduced by the requirement to design a diffused layer of greater width than the necessary minimum width in order to ensure a diffused layer width that sufficiently lowers resistance of the buried N.sup.+ bit lines despite misalignment of this diffused layer.
To solve these problems, the method of forming a memory cell shown in FIG. 2 has been proposed in Japanese Patent Laid-open No. 233278/92 (Martin H. Manley, National Semiconductor Corporation). First, a polysilicon film for use as a floating gate is stacked on gate oxide film 4 overlying silicon substrate 1 and processed to gate form. Intergate insulation film 8 and a superposed polysilicon film are next successively formed, following which polysilicon side walls 9 are formed by a silicon film etch-back technique on the side walls of floating gate 5. Photoresist 10 is patterned so as to cover polysilicon side walls 9 on only the source side of the memory cell (Refer to FIG. 2A). Next, this photoresist 10 is used as a mask to remove the polysilicon side walls 9 on only the memory cell drain side, and after removing the photoresist 10, impurities are injected to form buried diffused layer 2 (Refer to FIG. 2B). Finally, a polysilicon film 7 for control gate use is formed on the element surface which is electrically connected with polysilicon side walls 9. A nonvolatile memory element can then be produced by carrying out subsequent steps such as normal wiring processes.
In this memory cell, the buried diffused layer 2 is self-aligned using floating gates 5 and polysilicon side walls 9 as a mask, thereby solving the previously described drawbacks, i.e., (1) variation in the electrical characteristics of series select transistors due to variation in channel length of the series select transistors; (2) variation in the series resistance of the buried bit lines; and (3) increase in the width of the diffused layer in order to lower resistance of the buried N.sup.+ bit lines.
However, photoresist mask 10, which is used in the process of removing only polysilicon side walls 9 on the memory cell drain side, must be formed so as to cover polysilicon side walls 9 on only the memory cell source side and not cover polysilicon side walls 9 on the drain side. As a result, the space between memory elements, i.e., the width of the buried N.sup.+ diffused layer, must be drawn wide enough to compensate for misalignment of photoresist mask 10. Therefore, due to this difficulty of reducing the spacing between elements, high packing density is difficult to achieve despite miniaturization of the memory elements themselves.
In addition, channel length of the series select transistors is also difficult to control because the residual amount of polysilicon side walls 9 on the memory cell source side, which defines the channel length, varies depending on the conditions of etch-back of the polysilicon film.
Furthermore, because the impurities in the buried N.sup.+ diffused layer are spread by thermal diffusion in heat treatments following formation of the layer, a small residual amount of the above-described polysilicon side walls 9 may cause extension of the source diffused layer as far as the edge of the floating gate of the memory cell, thereby possibly preventing formation of a series select transistor. To prevent this possibility, the residual amount of polysilicon side wall 9 must be made sufficiently great, thereby limiting the packing density of the elements.